Multi-way VLSI Circuit Partitioning Based on Dual Net Representation

Abstract

In this paper, we study the area-balanced multiway partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propose a general paradigm for multiway circuit partitioning based on dual net transformation. Given a netlist, we first compute a K-way partitioning of nets based on the HDN representation, and then transform the K-way net partition into a K-way module partitioning solution. The main contribution of our paper is in the formulation and solution of the K-way module contention (KMC) problem, which determines the best assignment of the modules in contention to partitions while maintaining user-specified area requirements when we transform the net partition into a module partition. Under a natural definition of binding function between nets and modules, and preference function between partitions and modules, we show that the K-MC problem can be reduced to a min-cost max-flow problem. We present an efficient solution to the K-MC problem based on network flow computation. We apply our dual transformation paradigm to the well-known K-way Fiduccia-Mattheyses (FM) partitioning algorithm (K-FM) and show that the new algorithm, named K-DualFM, reduces the net cutsize by 20% to 31% compared with the K-FM algorithm. We also apply the same paradigm to the K-maximum fanout-free cone (MFFC)-FM algorithm, a K-FM algorithm based on MFFC clustering, and show that the resulting algorithm, K-DualMFFC-FM reduces the net cutsize by 15% to 26% compared with K-MFFC-FM. Furthermore, we compare the K-DualFM algorithm with EIG1 and Paraboli, two recently proposed spectral-based bipartitioning algorithms. We showed that K-DualFM reduces the net cutsize by 56% on average when compared with EIG1 and produces comparable results with Paraboli.