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Multi-Way VLSI Circuit Partitioning

Agrawal, P. and Narendran, B. and Shivakumar, N. (1996) Multi-Way VLSI Circuit Partitioning. Technical Report. Stanford InfoLab. (Publication Note: Proceedings of 9th International Conference on VLSI Design, Bangalore, India, Jan'96)




Partitioning is one of the critical phases of hierarchical design processes like VLSI design. Good partitioning techniques can positively influence the performance and cost of a VLSI product. This paper proposes a partitioning algorithm with a new cost metric. viewed from a VLSI layout point of view our cost metric minimizes the average delay per net. It can also be interpreted as achieving the minimum number of vias per net. This paper highlights how the seemingly slight difference between our metric and others could cause partitions to be evaluated considerably differently. Experimental results show that in addition to the expected improvements we get on our metric, the proposed algorithm does well on the traditional nets cut metric as well.

Item Type:Techreport (Technical Report)
Uncontrolled Keywords:VLSI, CAD, Partitioning, Circuit
Subjects:Computer Science
Related URLs:Project Homepage
ID Code:177
Deposited By:Import Account
Deposited On:25 Feb 2000 16:00
Last Modified:08 Dec 2008 14:48

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